1. Field of the Invention
The invention relates to a semiconductor integrated circuit, and more particularly, to a current DAC (Digital-Analog Converter) cell circuit, which can reduce the voltage fluctuations during current switching so as to make the output voltage reaching stable quickly. Also we can reduce the current spike when large current switching instantaneously by controlling the slew rate of output current.
2. Description of the Related Art
Recently, owing to the enhancing efficiency of the microprocessor for the personal computer, the demands for image processing are getting higher. Consequently, the digital-to-analog converters (DACs) are getting more important for the image display. However, when the operation frequency of the microprocessor is getting higher, the demands for the precision and speed of the DAC are getting stricter. It is quite important to perform digital-to-analog conversion with fast settling and high accuracy.
FIG. 1 is a conventional current-type DAC cell circuit. Referring to FIG. 1, the DAC cell circuit includes a PMOSFFT 11 and a pair of PMOSFETs 12 and 13. The PMOSFET 11 serves as a constant current source to provide a constant current Is for the DAC cell circuit and is controlled by an input signal Vbp with constant voltage. The pair of PMOSFETs 12 and 13 serves as a current switch pair and the sources of the PMOSFETs 12 and 13 are both connected to the drain of the PMOSFET 11, and the drains of the PMOSFETs 12 and 13 are connected to resistors 14 and 15, respectively. The switching operations of the PMOSFETs 12 and 13 are controlled by the control signals Q and QB, which are input to the gates of the PMOSFETs 12 and 13, respectively. The control signal QB is the logic reverse signal of the control signal Q. The switches are PMOSFETs, which are low active. When the control signal Q is low, the DAC cell circuit outputs an analog current and the current signal is translated to output voltage through resistor 14. And when the control signal Q is high then the control signal QB is low, the DAC cell circuit outputs an analog current to the dummy load resistor 15. The control signals Q and QB are a pair of control signals with non-overlap timing control, as shown in FIG. 2.
The operation principle of the DAC cell circuit in FIG. 1 is described as follows. When DAC cell current is switched from dummy load to output, the control signal Q is changed from High to Low, the current I2 flowing trough the PMOSFET 12 is changed from 0 to Is. In order to avoid reducing speed of the DAC cell circuit during switching, it is necessary to use the control signals with non-overlap timing control, for example the control signals Q and QB as shown in FIG. 2. The non-overlap timing control means that one switch must be turned on 1st and the other switch then can be turned off. The PMOSFET 12 is turned ON first, and next the PMOSFET 13 is turned OFF, and then the current I2 flowing through the PMOSFET 12 is changed from 0 to Is. If the control signals Q and QB are not non-overlap timing signals, the PMOSFETs 12 and 13 of the switch pair may be turned off simultaneously during the current switching. Then, the voltage Vcs of the common source node of the switch pair is instantly pulled toward voltage Vcc through the PMOSFET 11. The unnecessary error circuit operation makes the transistor 11 be turned off. Therefore, the DAC cell circuit has to spend additional time to discharge the voltage Vcs at the common source node from Vcc to a stable potential. This may limit the operation speed of the DAC cell circuit, and thus it is necessary to use the control signals with non-overlap timing control.
However, even if the DAC cell circuit is controlled by the control signals with non-overlap timing control, voltage fluctuation at the common source node in the switch pair of the DAC cell circuit may still exist. This is because the operation method using the control signals with non-overlap timing control has to ensure that the PMOSFETs 12 and 13 of the switch pair cannot be turned off simultaneously. That is, one of the PMOSFETs has to be turned on and then the other PMOSFET can be turned off. At that moment when the two PMOSFETs 11, 12 are simultaneously turned on, the current flowing through the PMOSFETs 11, 12 is only equal to one half of current of the constant current source. The gate-source voltage VGS of the two PMOSFETs is smaller than the gate-source voltage VGS when one PMOSFET is turned on. This may still cause the voltage vibration at the common source node, thereby limiting the operation speed of the DAC cell circuit, as shown in FIG. 2.